1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor array substrate, and more particularly, to a method of manufacturing a thin film transistor array substrate capable of reducing the number of a mask process.
2. Description of the Related Art
In general, a liquid crystal display device represents an image by means of adjusting a transmittance of a liquid crystal material using an electric field. For this purpose, the liquid crystal display device comprises a liquid crystal display panel in which the liquid crystal cells are arranged in a matrix pattern, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes the thin film transistor array substrate and a color filter array substrate facing each other, a spacer located for fixedly maintaining a cell gap between two substrates and a liquid crystal injected into the cell gap.
The thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed as a switching device at every crossing of the gate lines and the data lines, a pixel electrode connected to the thin film transistor substantially defining a liquid crystal cell, and an alignment film applied to the substrate. The gate lines and the data lines receive signal from the driving circuits through each of their respective pad parts. The thin film transistor, in response to a scan signal supplied to a gate line, supplies to the pixel electrode a pixel voltage signal applied to the data line.
The color filter array substrate includes a color filter formed to correspond to the liquid crystal cells, a black matrix for reflecting external light and separating between the color filters, a common electrode for commonly supplying a reference voltage to the liquid crystal cells, and the alignment film applied to the substrate.
The liquid crystal display panel is fabricated by combining the thin film transistor array substrate and the color filter array substrate which are separately manufactured, injecting the liquid crystal material between the substrates, and sealing the substrates having the liquid crystal material between them.
In such a liquid crystal display device, thin film transistor array substrate fabrication involves a semiconductor process and requires a plurality of mask processes, which complicates the manufacturing process. This is a major factor in the manufacturing cost of the liquid crystal display panel. In order to solve this, a thin film transistor array substrate has been developed with a goal of reducing the number of mask processes. This is because one mask process includes a plurality of sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection processes and the like. Recent development efforts have resulted in a four-round mask process that eliminated one mask process from an existing five-round standard mask process.
FIG. 1 is a plan view illustrating a thin film transistor array substrate adopting a related art four-round mask process, and FIG. 2 is a sectional view illustrating the thin film transistor array substrate taken along line I–I′ in FIG. 1.
The thin film transistor array substrate, shown in FIG. 1 and FIG. 2, includes gate lines 2 and data lines 4 crossing with each other and having a gate insulation film between them on a lower substrate 42, a thin film transistor 6 formed at every crossing, and a pixel electrode 18 formed in the cell region substantially defined by the crossing of the gate lines 2 and data lines 4. Further, the thin film transistor array substrate includes a storage capacitor 20 formed at an overlapped part of the pixel electrode 18, a pre-stage gate line 2, a gate pad part 26 connected to the gate line 2, and a data pad part 34 connected to the data line 4.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 18, and an active layer 14 of semiconductor pattern 47, which defines a channel between the source electrode 10 and the drain electrode 12 and overlapping the gate electrode 8. Referring to FIG. 2, the active layer 14 overlaps with a lower data pad electrode 36, a storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12, and further includes a channel portion defined between the source electrode 10 and the drain electrode 12. Further formed on the active layer 14 are the lower data pad electrode 36, the storage electrode 22, the data line 4, the source electrode 10, the drain electrode 12 and an ohmic contact layer 48 of the semiconductor pattern 47 for making an ohmic contact. The thin film transistor 6 responds to the gate signal supplied to the gate line 2 and applies a pixel voltage signal supplied to the data line 4 to the pixel electrode 18.
The pixel electrode 18 is generally connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 16 passing through a passivation film 50. The pixel electrode 18 generates a potential difference along with the common electrode formed on the upper substrate (not shown) when a pixel voltage is applied to the electrode. By this potential difference, the liquid crystal molecules located between the thin film transistor substrate and the upper substrate rotate due to the molecules' dielectric anisotropy, and makes incident light through the pixel electrode 18 from the light source (not shown) transmit to the upper substrate.
The storage capacitor 20 includes a pre-stage gate line 2; a storage electrode 22 overlapping the pre-stage gate line 2 having a gate insulating film 44; the active layer 14 and the ohmic contact layer 48 between the active layer 14 and the storage electrode 22. The pixel electrode 18, which connects to the storage electrode 22 through contact hole 24, is formed on the passivation film 50 and overlaps the storage electrode 22. The storage capacitor 20 substantially maintains the pixel voltage applied to the pixel electrode IP until a next pixel voltage is applied.
The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad part 26 includes a lower gate pad electrode 28 extending from the gate line 2 and an upper gate pad electrode 32 connected to the lower gate pad electrode 28 via a third contact hole 30 passing through both of the gate insulating film 44 and the passivation film 50. The data line 4 is connected to the data driver (not shown) through the data pad part 34. The data pad part 34 includes the lower data pad electrode 36 extending from the data line 4 and an upper data pad electrode 40 connected to the lower data pad electrode 36 via a fourth contact hole 38 passing through the passivation film 50.
The thin film transistor substrate having the above-mentioned configuration is formed through the use of the four-round mask process, according to the related art.
FIGS. 3A to 3D are sectional views sequentially illustrating a method of manufacturing the thin film transistor substrate.
Referring to FIG. 3A, gate patterns are formed on the lower substrate 42.
On the lower substrate 42, a gate metal layer is formed by a deposition method such as a sputtering method. Subsequently, the gate metal layer is then patterned by a photolithography and an etching process using a first mask to thereby form the gate patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28. A gate metal, which may include a chrome (Cr), a molybdenum (Mo), an aluminium (Al) and the like are used in the form of a single-layer structure or a double-layer structure.
Referring to FIG. 3B, the gate insulating film 44, the active layer 14, the ohmic contact layer 48 and source/drain patterns are sequentially formed on the lower substrate 42 provided with the gate pattern.
The gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially formed on the lower substrate 42 having the gate patterns thereon by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD) or sputtering.
A photo-resist pattern is formed on the source/drain metal layer by a photolithography process using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than the other source/drain patterns.
Subsequently, the source/drain metal layer is then patterned by a wet etching process using the photo-resist pattern, to thereby form source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the amorphous silicon layer and the n+ amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby form the semiconductor pattern 47 including the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height is removed from the channel portion by an ashing process and thereafter the source/drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 from the drain electrode 12.
Thereafter, a remainder of the photo-resist pattern left on the source/drain pattern is removed using a stripping process.
The gate insulating film 44 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). A metal for the source/drain pattern includes a molybdenum (Mo), a titanium (Ti), tantalum (Ta) or a molybdenum alloy.
Referring to FIG. 3C, the passivation film 50 includes first to fourth contact holes 16, 24, 30 and 38, which are formed on the gate insulating film 44 having the source/drain patterns.
The passivation film 50 is entirely formed on the gate insulating film 44 having the source/drain patterns by a deposition technique such as a plasma enhanced chemical vapor deposition (PECVD). The passivation film 50 is patterned by a photolithography and an etching process using a third mask to thereby form the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed in such a manner to pass through the passivation film 50 and expose the drain electrode 12, whereas the second contact hole 24 is formed in such a manner to pass through the passivation film 50 and expose the storage electrode 22. The third contact hole 30 is formed in such a manner to pass through the passivation film 50 and the gate insulating film 44 and expose the lower gate pad electrode 28, whereas the fourth contact hole 38 is formed in such a manner to pass through the passsivation film 50 and expose the lower data pad electrode 36.
The passivation film 50 is generally made of an inorganic insulating material such as a material of the gate insulating film 44 or an organic insulating material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).
Referring to FIG. 3D, transparent electrode patterns are formed on the passivation film 50. More specifically, a transparent electrode material is entirely deposited on the passivation film 50 by a deposition technique such as sputtering and the like. Then, the transparent electrode material is patterned by a photolithography and an etching process using a fourth mask, to thereby provide the transparent electrode patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 and is electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping a pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. The transparent electrode material may be made of an indium-tin-oxide (ITO), a tin-oxide (TO) or an indium-zinc-oxide (IZO).
As described above, the related art thin film transistor array substrate and the manufacturing method thereof adopts a four-round mask process, thereby reducing the number of manufacturing processes in comparison with the five-round mask process and hence reducing a manufacturing cost accordingly. However, since the four-round mask process still has a complex manufacturing process and a limitation in reducing the manufacturing cost, there is a need for an approach that is capable of further simplifying the manufacturing process and further reducing the manufacturing cost.